Job Overview:
This is a great opportunity to join Arm’s Solutions Test Team, working with emerging process technologies and the latest offerings across Cloud, Infrastructure, IoT, and Automotive segments.
We are seeking a Pre-Silicon DFT / Design Verification Engineer with an ATE test focus. This role sits at the intersection of DFT, DV, Manufacturing Test, and ATE enablement, with emphasis on ensuring that pre-silicon design and verification choices translate cleanly and efficiently into high-volume ATE test patterns.
The engineer will contribute to scan/ATPG readiness, testability verification, early test coverage analysis, test-mode validation, and production test collateral readiness. This role works closely with DFT, DV, Design, Product Engineering, and ATE teams to reduce post-silicon risk, improve test robustness, and lower the cost of test.
The role requires an execution-oriented engineering focus across areas such as pre-silicon DFT verification, ATPG readiness, scan and MBIST validation, gate-level and timing-aware simulation, pattern quality analysis, and ATE-friendly test collateral handoff.
Responsibilities:
- Support pre-silicon DFT verification for logic and memory test structures, including scan chains, scan compression, MBIST, and test access networks.
- Verify ATE-friendly test architectures and ensure compatibility with production ATE flows, including Advantest V93000 / EXAScale SMT8 and Teradyne UltraFLEX environments.
- Review RTL and gate-level netlists for ATPG readiness, identifying structural issues that could impact coverage, pattern quality, test time, power, yield, or manufacturability.
- Execute and analyze pre-silicon ATPG runs to assess early test coverage, pattern quality, pattern volume, and production readiness.
- Develop and maintain test-oriented DV environments to validate DFT logic behavior, test modes, constraints, clocks, resets, and power-domain interactions.
- Run RTL, gate-level, and timing-aware simulations, including SDF-backed scenarios where applicable, to validate scan, reset, and test-mode robustness.
- Debug test-mode failures and coordinate fixes with logic, DFT, DV, and design teams.
- Collaborate with ATE and Product Engineering teams to support seamless handoff of pre-silicon test collateral into wafer sort and final test flows.
- Support early definition of ATE test strategies for WS/FT, including scan, MBIST, functional assist, and other DFT-based test content.
- Identify and mitigate test-time, pattern data volume, tester memory, and power risks early in the design cycle.
- Assist in defining test coverage targets, pattern quality expectations, and DFT/test sign-off criteria.
- Contribute to automation scripts and flows using Tcl, Python, Bash, or similar languages to improve pre-silicon test validation efficiency.
- Support version-controlled management of DFT, ATPG, simulation, and test collateral using Git, SVN, or similar workflows.
- Assist in regression, coverage, reporting, and debug automation for DFT/DV test validation.
Required Skills and Experience:
- Bachelor’s degree or equivalent experience in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field.
- 8–10+ years of experience in DFT, Design Verification, Manufacturing Test, or semiconductor test-related roles.
- Solid understanding of scan architectures, ATPG concepts, scan compression, and pattern generation flows.
- Knowledge of MBIST and basic memory test principles.
- Understanding of test modes, resets, clocks, constraints, power domains, and their impact on DFT operation.
- Hands-on experience with Siemens Tessent ATPG, DFT, diagnosis, or equivalent DFT tools.
- Experience with RTL and gate-level simulation using industry simulators such as VCS, Questa, or equivalent.
- Ability to debug scan, ATPG, MBIST, reset, clocking, and test-mode failures in RTL or gate-level environments.
- Working knowledge of Linux / Unix environments.
- Proficiency in at least one scripting language such as Tcl, Python, or Bash.
- Demonstrated ability to work across DFT, DV, Design, Product Engineering, and ATE teams.
- Strong analytical, debug, and problem-solving skills with attention to test robustness and manufacturability.
“Nice To Have” Experience:
- Exposure to ATE platforms such as Advantest V93000 / EXAScale SMT8, SMT7.
- Experience with pre-silicon to post-silicon test correlation.
- Familiarity with power-aware ATPG, scan compression, scan insertion constraints, or low-power test validation.
- Knowledge of yield, diagnosis, silicon bring-up, characterization, or failure analysis flows.
- Experience working across multiple advanced process nodes.
- Familiarity with pattern conversion flows, including STIL or tester-ready pattern formats.
- Exposure to ATE production or characterization test flows, including scan, MBIST, functional assist, sensors, or related test content.
- Experience with regression automation, coverage reporting, and DFT/test collateral quality checks.
- Knowledge of IEEE 1149, 1500, 1687, or 1838 standards.
- Familiarity with Streaming Scan Network, scan diagnostics, or production diagnosis methodologies.
- Experience with data analysis tools such as Excel, Tableau, JMP, YieldExplorer, or equivalent.
- Exposure to wafer sort, final test, probe card, loadboard, socket, or thermal control interface considerations.
At Arm, we believe progress happens when people are empowered to think bigger and push beyond what seems possible. Our 10x mindset is about curiosity, ambition, and creating impact through technology used by millions.
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Accommodations at Arm
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Hybrid Working at Arm
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Equal Opportunities at Arm
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