Overview

The ARM Solutions Engineering Technology and IP team is seeking talented IP Verification Engineers across multiple experience levels, from engineers developing their verification expertise through to experienced Staff Engineers capable of owning complex IP and subsystem verification programs.

These roles provide opportunities to work across a broad portfolio of technologies, including high-speed I/O, PCI Express (PCIe), DDR and memory interfaces, interconnect, compute and control subsystems, and security IP.

Depending on experience and role level, engineers may contribute to verification environment development, test creation and debug, own verification of an IP or major feature, lead subsystem-level verification, or provide technical direction across projects and teams.

You will collaborate with architecture, design, implementation, firmware, performance, and SoC integration teams to deliver robust, reusable, and production-ready IP for next-generation SoCs.

Opportunities Across Experience Levels

We are hiring for multiple individual-contributor positions and will align responsibilities with the successful candidate's experience, technical depth, and ownership capability.

Verification Engineer

Engineers at this level will typically:

• Develop tests, sequences, assertions, checkers, and functional coverage.
• Debug simulation and regression failures with support from experienced team members.
• Contribute to SystemVerilog/UVM verification environments.
• Translate defined requirements and test-plan items into verification collateral.
• Support coverage analysis, regression triage, and bug investigation.
• Build knowledge of IP architecture, protocols, verification methodology, and product-development processes.

Senior Verification Engineer

Senior engineers will typically:

• Own verification of significant IP features or functional areas.
• Develop verification strategies, test plans, coverage models, and reusable verification components.
• Lead complex debug involving RTL, testbench, firmware, protocol, and integration behavior.
• Drive functional, code, assertion, and scenario coverage toward closure.
• Review specifications and designs to identify verification risks, ambiguities, and corner cases.
• Mentor less-experienced engineers and improve verification methodology and automation.
• Coordinate verification activities with design, architecture, firmware, and implementation teams.

Staff Verification Engineer

Staff engineers will typically:

• Lead end-to-end verification of complex IPs, subsystems, or major functional areas.
• Define verification architecture, methodology, reuse strategy, and sign-off criteria.
• Identify technical and schedule risks early and drive mitigation across teams.
• Influence IP architecture and design through verification insights, modeling, and early analysis.
• Lead verification planning across projects, configurations, and customer use cases.
• Drive reuse of verification collateral from IP level through subsystem and SoC integration.
• Provide technical guidance, mentor engineers, and lead complex debug and coverage-closure efforts.
• Collaborate with engineering and program teams on execution strategy, dependencies, risks, and delivery commitments.
• Improve verification quality, scalability, automation, and engineering practices across the team.

Responsibilities

Responsibilities will vary by role level and may include:

• Developing verification strategies, test plans, and coverage plans from architecture and design specifications.
• Building and maintaining reusable SystemVerilog/UVM verification environments, agents, scoreboards, reference models, assertions, and coverage models.
• Verifying IP and subsystems such as high-speed interfaces, PCIe, DDR and memory controllers, interconnect, embedded processor systems, and security hardware.
• Creating constrained-random, directed, protocol-compliance, error-injection, low-power, and performance-oriented tests.
• Driving functional, code, assertion, and scenario coverage to closure.
• Debugging failures across RTL, testbench, firmware, and system-level interactions.
• Verifying multi-clock, multi-reset, and multi-power-domain behavior.
• Supporting hardware and firmware co-verification, including boot, initialization, configuration, interrupt, error-handling, and recovery flows.
• Contributing to verification automation, regression infrastructure, dashboards, and continuous-integration flows.
• Improving verification methodologies, reusable components, coding practices, and sign-off criteria.
• Participating in architecture, specification, design, test-plan, and coverage reviews.
• Mentoring engineers and providing technical guidance appropriate to the role level.

Required Skills and Experience

The depth and breadth expected in each area will depend on the position level.

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• Understanding of digital design, Verilog/SystemVerilog RTL, and simulation-based verification.
• Experience with SystemVerilog, UVM, or comparable verification methodologies.
• Experience with verification planning, stimulus development, functional coverage, assertions, scoreboards, and debug.
• Understanding of SoC and IP architecture, including clocking, reset, interrupts, address maps, memory-mapped interfaces, and system integration.
• Familiarity with one or more protocols or technology areas such as AXI, AHB, APB, CHI, PCIe, DDR, high-speed I/O, interconnect, processor subsystems, or security IP.
• Experience with scripting or programming languages such as Python, Perl, TCL, Bash, C, or C++.
• Ability to collaborate across teams and communicate technical information clearly.
• Demonstrated ownership and technical leadership appropriate to the experience level of the role.

Desirable Skills and Experience

Experience in one or more of the following areas would be beneficial:

• PCIe controllers, transaction layers, link management, protocol compliance, and error recovery.
• DDR controllers, memory PHY interfaces, training, initialization, scheduling, and reliability features.
• High-speed serial interfaces, coherent or non-coherent interconnect, cache, and memory subsystems.
• Security IP, including hardware roots of trust, secure boot, cryptography, key management, lifecycle management, access control, and secure debug.
• Embedded processor systems and hardware/firmware co-verification.
• Low-power verification using UPF, power-state modeling, isolation, retention, and reset sequencing.
• Formal verification, assertion-based verification, Portable Stimulus, reference models, emulation, or acceleration.
• Verification at IP, subsystem, and SoC levels.
• Performance verification, traffic modeling, stress testing, and bottleneck analysis.
• Familiarity with ARM-based designs and ARM system architectures.

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Accommodations at Arm

At Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.

Hybrid Working at Arm

Arm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.

Equal Opportunities at Arm

Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.