Role Summary
Our Solutions Engineering Physical IP team comprises some of the industry’s leading experts in deep submicron circuit design. This position is a wonderful opportunity for you to work with our custom standard cell design engineering team on innovative technologies. Your work will have a significant lasting impact as the designs will be used in Solutions Engineering products servicing the infrastructure, client, automotive, and IoT market segments.
In this role, you will be responsible for the layout development of Arm custom standard cells in the latest, sub-3nm process technology nodes. The ideal candidate will be an expert in standard cell layout, physical verification, and automation techniques. You will work in close collaboration with the circuit design team to provide optimally tuned layout, and validate them through QA flows that use a variety of tools. This role is crucial in delivering high-performance, area-optimized, and DRC-clean logic libraries for next-generation SoCs and custom digital IPs.
Key Responsibilities
- Independently develop transistor-level physical layouts from circuit schematics.
- Create and interpret stick diagrams and determine efficient transistor placement and routing strategies.
- Optimize device placement, diffusion sharing, routing and pin accessibility to achieve compact and robust layouts.
- Perform DRC, LVS and physical-verification debugging and independently resolve routine violations.
- Understand and apply requirements from technology Design Rule Manuals (DRMs) and established layout guidelines.
- Perform layout modifications resulting from schematic, design-rule or methodology changes.
- Understand parasitic resistance and capacitance introduced by physical implementation and their effect on circuit behaviour.
- Apply established layout techniques to improve power, performance and area (PPA).
- Consider reliability requirements such as current density, electromigration and routing robustness during implementation.
- Perform layout quality checks and participate in peer reviews.
- Review straightforward layout work produced by other engineers where required.
- Work with circuit designers to identify practical solutions to layout-related implementation challenges.
- Manage assigned workload, communicate progress and identify potential technical or schedule risks.
- Support development of less-experienced engineers through knowledge sharing and occasional on-the-job guidance.
- Contribute to continuous improvement of layout practices and team workflows.
Technical Skills / Expertise
- CMOS transistor-level circuit layout
- Schematic interpretation
- Stick-diagram development
- Transistor placement and diffusion optimization
- DRC and LVS
- Physical-verification debugging
- Design Rule Manual interpretation
- Parasitic resistance and capacitance
- Basic EM/current-density considerations
- Layout-dependent effects
- PPA-aware physical implementation
- Semiconductor manufacturing/process fundamentals
- Practical AI-tool proficiency is required. Candidates should be able to use approved AI assistants to accelerate technical investigation, generate and refine Python/Tcl/SKILL scripting ideas, analyze logs and verification results, improve documentation and automate repetitive engineering tasks, while independently validating AI-generated outputs for technical correctness and complying with data-security and responsible-AI requirements.
Experience with industry-standard custom-layout and physical-verification environments such as Cadence Virtuoso, Synopsys Custom Compiler, Siemens Calibre or equivalent tools is desirable/expected depending on seniority.
What We Are Looking For
- Complete straightforward layout assignments with minimal or no supervision.
- Take ownership of assigned layouts from initial implementation through physical-verification closure.
- Make sound engineering decisions using established methodology and previous experience.
- Independently troubleshoot common layout and verification problems.
- Recognize when a problem requires specialist or senior-level input.
- Balance layout quality, area, performance and schedule requirements.
- Communicate technical information clearly within the engineering team.
- Work effectively with circuit designers and related engineering teams.
- Provide constructive peer-review feedback.
- Consistently deliver accurate, high-quality work within agreed schedules.
- Use AI tools as a normal engineering productivity aid while retaining ownership of technical decisions, verification and final deliverables.
Education / Experience :
Bachelor's or Master's degree in Electronics, Electrical Engineering, VLSI, Microelectronics, Semiconductor Engineering or equivalent practical experience. Professional experience in custom IC, standard-cell, memory, analog or related transistor-level layout design is preferred.
“Nice To Have” Skills and Experience :
- Exposure to physical design implementation flow
#LI-BB1
Accommodations at Arm
At Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.
Hybrid Working at Arm
Arm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.
Equal Opportunities at Arm
Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.