We are seeking a highly skilled engineer with deep expertise in multi-die and chiplet-based system integration across 2D, 2.5D, and 3.5D packaging technologies. The candidate will be responsible for bump and floor-planning, package routing feasibility, interposer and substrate design, chip-level integration, and system-level planning. This role involves close collaboration with Arch, RTL, foundry/OSAT partners, silicon design, packaging, thermal, and mechanical teams to deliver high-performance, manufacturable solutions for next-generation heterogeneous integration platforms.
Responsibilities:
- Develop and validate interposer routing and partitioning strategies for 2.5D/3.5D architectures.
- Lead bump and floor-planning for multi-die and chiplet configurations.
- Perform chip-level and package-level floor-planning, including IO assignment and interconnect planning.
- Conduct package routing feasibility studies for sophisticated packaging solutions (organic, silicon interpoer, fan-out, etc.).
- Drive chip planning and system-level design across multiple dies and substrates.
- Collaborate with EDA, mechanical, and thermal teams for package thermal modeling and optimization.
- Work with foundry and OSAT partners to define design rules and manufacturing constraints.
- Support signal integrity (SI), power integrity (PI), and thermal studies for package-level performance.
- Supply to EDA tool flows for chip-package-system (CPS) co-design and co-optimization.
- Provide technical inputs during architecture definition and early feasibility studies.
- Document design methodology and support multi-functional teams through design reviews.
Required Skills and Experience :
- 5+ years of experience in System floor-planning, SoC integration along with advanced packaging expertise (2.5D/3D).
- Shown experience in bump planning, RDL routing, interposer design, and multi-die integration.
- Required work experience needed on “3D-IC early PDN analysis flow"
- Hands-on experience with EDA tools such as Cadence 3DIC/SiP/Allegro, Synopsys 3DIC Compiler, Ansys, or similar.
- Strong understanding of signal integrity, power integrity, and thermal constraints in advanced packages.2.5
- Familiarity with manufacturing processes, material stack-ups, and assembly flows for advanced packages.
- Excellent multi-functional collaboration and problem-solving skills.
“Nice To Have” Skills and Experience :
- Exposure to system-level thermal modeling tools (e.g., Ansys Icepak, FloTHERM).
- Understanding of mechanical stress and warpage analysis for multi-die assemblies.
- Ability to script and automate workflows using Python, TCL, or SKILL.
- Familiar with Cadence/Synopsys/Mentor tools.
Our 10x mindset guides how we engineer, collaborate, and grow. Understand what it means and how to reflect 10x in your work:https://careers.arm.com/en/10x-mindset
Salary Range:
$241,100-$326,100 per yearWe value people as individuals and our dedication is to reward people competitively and equitably for the work they do and the skills and experience they bring to Arm. Salary is only one component of Arm's offering. The total reward package will be shared with candidates during the recruitment and selection process.
Accommodations at Arm
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Hybrid Working at Arm
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Equal Opportunities at Arm
Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.