As a part of Arm's Solutions Engineering group we like to think we are not just crafting sophisticated SoCs, but we are defining future chip design techniques. Not only do we improve the power, performance and system integration of our products, but we also craft the design flows, influence Electronic Design Automation (EDA) tools and build the knowledge base that makes custom SoC and CPU chip design possible. At Arm, our work goes beyond multiple divisions where we drive improved implementation for Arm and our partners. A key component of this is the development of comprehensive implementation and analysis methodologies.
Key Responsibilities
- Define and implement SoC-level floor plans for advanced process nodes (5nm and below).
- Collaborate with SoC architects, RTL, and implementation teams to translate functional architecture into optimal physical partitioning.
- Develop and manage floorplan constraints, including macro placement, power grid planning, and IO ring integration.
- Analyze utilization, routing congestion, and timing feasibility, iterating with design and PD teams to refine layout.
- Ensure well-balanced floorplans that meet PPA, power domain, and routing requirements.
- Partner with package, DFT, and physical verification teams to ensure cohesive integration across the chip boundary.
- Support ECOs, floorplan updates, and late-stage convergence to ensure a robust signoff path.
- Contribute to the development of automation scripts and internal tools to improve floorplan exploration and quality-of-results (QoR).
- Participate in design reviews and drive best practices across projects and teams.
Required Skills and Experience
- 4+ years of hands-on experience in SoC Physical Design, with a primary focus on floorplanning.
- Proficiency with EDA tools such as Cadence Innovus, Synopsys ICC2, or Fusion Compiler.
- Deep understanding of:
- Hierarchical SoC design and partitioning
- Macro and memory placement strategies
- Power domain and clock domain planning
- Floorplan constraint generation and block-level integration
- Proven ability to resolve timing, IR drop, and congestion challenges during floorplan and implementation.
- Experience working on advanced technology nodes (7nm / 5nm / 3nm).
- Strong scripting skills in Tcl, Python, or Perl for design automation.
- Familiarity with LEF/DEF, UPF, and GDSII formats.
In Return:
Our offices are outstanding places to collaborate. If you are interested, but unsure whether you tick all the boxes, we still would love you to reach out! We are keen to welcome versatile people into Arm!
Our 10x mindset guides how we engineer, collaborate, and grow. Understand what it means and how to reflect 10x in your work:https://careers.arm.com/en/10x-mindset
Accommodations at Arm
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Hybrid Working at Arm
Arm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.
Equal Opportunities at Arm
Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.