Role Summary
Our Solutions Engineering Physical IP team comprises some of the industry’s leading experts in deep submicron circuit design. This position is a wonderful opportunity for you to work with our custom standard cell design engineering team on innovative technologies. Your work will have a significant lasting impact as the designs will be used in Solutions Engineering products servicing the infrastructure, client, automotive, and IoT market segments.
In this role, you will be responsible for the layout development of Arm custom standard cells in the latest, sub-3nm process technology nodes. The ideal candidate will be an expert in standard cell layout, physical verification, and automation techniques. You will work in close collaboration with the circuit design team to provide optimally tuned layout, and validate them through QA flows that use a variety of tools. This role is crucial in delivering high-performance, area-optimized, and DRC-clean logic libraries for next-generation SoCs and custom digital IPs.
Key Responsibilities
- Layout design of logic standard cells (inverters, muxes, flops cells, complex logic gates) optimized for performance, area, and power.
- Work with automation and QA teams to support library validation flows.
- Collaborate with circuit designers to understand schematics and translate them into clean, compact layouts.
- Drive design rule clean (DRC) and layout vs. schematic (LVS) closure using industry-standard verification tools (e.g., Calibre ).
- Perform layout debugging and root-cause analysis for DRC, LVS, and other physical sign-off issues.
- Handle cell abutment, cell profiling, and cell integration constraints for logic libraries.
- Address layout-dependent effects (LDE) and double patterning/EUV compliance in advanced nodes.
- Review and debug standard cell physical views (LEF, GDS, abstract views) for integration into digital flows.
- Automate layout QA, regression checks, and PDK-driven layout verifications using scripts (e.g., SKILL, Python).
- Participate in library quality audits and delivery cycles including signoff package creation and documentation.
Required Skills and Experience
- 3+ years of custom layout experience in logic standard cell development.
- Proven track record of working at 5nm, 3nm, or 2nm nodes with FinFET/GAA-based technologies.
- Proficiency in Cadence Virtuoso.
- Deep understanding of advanced DRC rules, LVS methodologies, and multi-patterning constraints.
- Solid experience in cell layout optimization for PPA (Power, Performance, Area).
- Strong grip on pin accessibility, cell architecture trade-offs, and physical synthesis-aware design.
- Automate layout-related tasks and workflows using scripting languages like Python, PERL, SKILL, and TCL.
- Maintain accurate documentation of layout designs, changes, and verification results.
- Working knowledge of version control, configuration management, and flow automation
- Make effective use of AI tools and automation to improve productivity, accelerate learning, and enhance the quality of technical solutions
- Strong documentation and communication skills to interface with cross-functional teams (PDK, design, QA).
- Stay updated on best practices for standard cell layout, design rules, and advanced node requirements.
“Nice To Have” Skills and Experience :
- Exposure to physical design implementation flow
#LI-PS2
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Accommodations at Arm
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Hybrid Working at Arm
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Equal Opportunities at Arm
Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.