Design Verification Engineer - Interconnect

Introduction

The Arm CoreLink CMN-600 Coherent Mesh Network is crafted for intelligent connected systems across a variety of applications including networking infrastructure, storage, server, HPC, automotive, and industrial solutions. The highly scalable mesh is optimized for Armv8-A processors and can be customized across a wide range of performance points. Our Austin-based team drives the specification, planning and development of UVM based testbenches to verify current and next generation designs. Our team completes verification for the entire interconnect solution including the transport layer, coherent interfaces, I/O bridges, registers and our coherent multi-chip link (CML).

What will I be accountable for

As a Design Verification Engineer, you would be delivering verification of one or more functional blocks at the unit or top level. Typical accountabilities include:

• Develop SystemVerilog/UVM testbenches for unit/top level.
• Build and maintain detailed verification plans.
• Generate and run test cases on logic simulation models.
• Debug functional errors in the RTL model using simulation and debug tools with an in-depth understanding of the microarchitecture.
• Define and implement functional coverage.
• Analysis of data from simulation runs using machine learning and data science techniques to drive efficient bug discovery and debug.
• Promote and demonstrate the Arm Core Beliefs and Behaviors.

Job Requirements

What skills, experience and qualifications do I need?

• Bachelor’s or Master’s degree in Computer Science or Electrical/Computer Engineering.
• Proven experience in pre-silicon verification/RTL design.
• Multiprocessing microarchitecture experience including knowledge of cache coherence and bus protocols (e.g. AMBA5 CHI, AMBA4 ACE or AXI).
• Previous experience in specification, creation, and debug of System Verilog/UVM constrained-random testbenches.
• Shown software engineering skills including understanding of object-oriented programming, data structures, and algorithms.
• Experience with functional coverage verification methods.
• Excellent professional knowledge of scripting languages such as Python or Perl
• Experience in Formal Verification testbenches is a plus.

What are the desired behaviors for this role?

At Arm, we are guided by our core beliefs that reflect our rare culture and guide our decisions, defining how we work together to surpass ordinary and shape extraordinary:

We not I

• Take daily responsibility to make the Global Arm community thrive
• No individual is responsible for the right answer. Brilliance is collective!
• Information is crucial, share it
• Realize that we win when we collaborate — and that everyone misses out when we don’t

Passion for progress

• Our differences are our strength. Widen and mix up your network of connections
• Difficult things can take unexpected directions. Stick with it
• Make feedback positive and expansive, not negative and narrow!
• The essence of progress is that it can’t stop. Grow with it and lead your own progress

Be your brilliant self

• Be quirky not egocentric
• Recognize the power in saying ‘I don’t know’

We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform crucial job functions, and to receive other benefits and privileges of employment. Please contact us to request accommodation.

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Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of any characteristic.